The invention relates to a method of erasing a non-volatile memory a number of bits at a time and to an integrated circuit that comprises a non-volatile memory.
U.S. patent application Ser. No. 5,844,842 discloses a Flash EEPROM device. The memory contains a matrix of memory transistors, organized in columns of transistors that have their main current channel connected in common to a bit-line for the column. Transistors in the same row have their control terminals connected together. In a flash memory information is stored by adjusting the threshold of memory transistors.
A typical memory transistor is a field effect transistor with a floating gate, whose threshold can be adjusted by injecting or removing charge carriers from the floating gate. Initially, the threshold of all memory transistors is at a first level, the erased level, which represents a first logical value. If a different logical value has to be stored at some locations in the memory, the threshold of the transistors that correspond to the relevant memory locations must be shifted. The memory shifts these thresholds to a second level, the programmed level. This is called programming.
In a read operation a transistor is selected from a column and the threshold of the selected transistor is sensed. For this purpose the memory supplies the selected transistor with a gate-source voltage between the programmed and erased level. As a result, the main current channel of the selected transistor will or will not conduct current, depending on whether the threshold of the transistor has or has not been programmed. The other transistors that are connected to the same column are prevented from delivering current to the bit-line. As a result, the logical value stored in the selected transistor can be determined from the current through the bit-line .
After the memory has been programmed with information the memory must be erased before different logical information can be stored. In a flash memory a block of memory transistors, for example a sector consisting of a number of rows of the matrix, is erased as a whole.
As described in the prior art, it is important that the threshold of all memory transistors is shifted back sufficiently to the erased level. To ensure this, the memory performs erasing in repeated steps. In each step threshold shifting signals are applied to all transistors in the sector. After each step the memory reads information successively from the different memory transistors in the sector. The erase steps are repeated until the read-out logic information level in all transistors corresponds to the erased level.